This present invention relates to polishing pads used in during chemical mechanical polishing.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against the polishing surface of a polishing pad, such as a rotating polishing disk or linearly advancing belt. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, which can include abrasive particles, is supplied to the surface of the polishing pad, and the relative motion between the substrate and polishing pad results in planarization and polishing.
Conventional polishing pads include “standard” pads and fixed-abrasive pads. A typical standard pad has a polyurethane polishing layer with a durable roughened surface, and can also include a compressible backing layer. In contrast, a fixed-abrasive pad has abrasive particles held in a containment media, and can be supported on a generally incompressible backing layer.
One objective of a chemical mechanical polishing process is to achieve topology uniformity across the substrate. Another object is to achieve polishing uniformity. If different areas on the substrate are polished at different rates, then it is possible for some areas of the substrate to have too much material removed (“overpolishing”) or too little material removed (“underpolishing”), which can result in non-uniform topography across the substrate.